1. Field of the Invention
The present invention relates to computer systems and, more specifically, to the input/output (I/O) subsystem of a computer system.
2. Background Information
Connected to most computer systems, including symmetrical multiprocessor (SMP) systems, are a plurality of peripheral components, such as disk drives, tape drives, graphics accelerators, audio cards, network interface cards (NICs), etc. The peripheral components are typically connected to an input/output (I/O) bus operating in accordance with a bus standard, such as Industry Standard Architecture (ISA), Extended ISA (EISA), and Peripheral Components Interface (PCI) bus standards. In most computer systems, the processor bus to which the processor(s), caches and the main memory are connected often runs at a higher speed than the I/O bus. Accordingly, a separate device, referred to as an I/O bridge, is used to interface between the processor and memory which are attached to the processor bus, and the peripheral components which are attached to the I/O bus. The I/O bridge basically moves transactions, e.g., reads and writes, between the processor bus and the I/O bus.
Recently, an extension to PCI, known as PCI-X, has been developed. The PCI-X bus standard, which provides for a bus width of 64 bits and a bus frequency of 133.3 MHz, represents a significant improvement over conventional PCI. In addition to the increase in bus operating speed, the PCI-X bus standard also defines several new features. Specifically, the PCI-X standard defines a new bus transaction phase called the xe2x80x9cattribute phasexe2x80x9d. The attribute phase uses a 36-bit attribute message which the initiator of a transaction drives onto the I/O bus immediately after the address phase. The attribute message contains several fields specifying information about the size of the transaction, the ordering of transactions, and the identity of the transaction initiator.
FIG. 1 is a highly schematic block diagram of a PCI-X attribute message 100 associated with a DWORD transaction. A DWORD is a 32-bit block of data aligned on four-byte boundaries. The attribute field 100 includes a 4-bit, byte enables field 102, which is set to indicate which of the four bytes of the DWORD contain valid data, a reserved (R) field 104, a no snoop (NS) field 106, a relaxed ordering (RO) field 108, and a 5-bit, tag field 110. The tag field 110 is used by the initiator of the bus transaction to uniquely identify up to 32 different sequences. A sequence is defined in the PCI-X standard as one or more transactions associated with carrying out a single, logical transfer, such as a read or write operation. The attribute message 100 further includes a requester bus number field 112, that contains the requester""s bus number in case the transaction crosses more than one I/O bus, a requester device number field 114, that contains the identification (ID) number assigned to the requester, a 3-bit, requester function number field 116, that contains an ID number assigned to the particular requesting function within the device, and a reserved field 118.
The requester function number field 116 is included to support multifunction peripherals connected to the I/O bus. An example of a multifunction peripheral is a combination Ethernet controller/disk controller disposed in a single physical device. Each separate function of a multifunction peripheral is encoded, typically during fabrication, with a respective function number. Devices which do not support multiple functions, including I/O bridges, are typically encoded with a single function number, e.g., xe2x80x9c000xe2x80x9d.
If the Ethernet controller part of the multifunction peripheral device drives an attribute message 100 onto the I/O bus, it loads its encoded function number, e.g., xe2x80x9c000xe2x80x9d, in field 116. If the disk controller part of the peripheral drives an attribute message 100 onto the I/O bus, it loads its encoded function number, e.g., xe2x80x9c001xe2x80x9d, in field 116. The function number field 116, among others, is used by a requesting device to help keep track of bus transactions that end up being xe2x80x9csplitxe2x80x9d as opposed to being completed at the time they are initiated.
Specifically, the PCI-X bus standard also provides support for xe2x80x9cSplit Transactionsxe2x80x9d, which allow a targeted device to delay the completion of a transaction initiated on the I/O bus, without tying up the bus or the requesting device. Suppose, for example, that a requesting device wishes to read data from a targeted device. The requesting device requests and gains control of the I/O bus. The requesting device then initiates the read transaction. As part of this process, the requesting device drives an attribute message 100 onto the I/O bus, which specifies its device number, its function number, and a selected tag value, among other information. If the targeted device is able to accept the transaction, but must delay the delivery of the data, it responds to the requesting device with a Split Response. The I/O bus can then be used to transfer other transactions by the requesting device or by other devices. When the targeted device is ready to deliver the data, it places a Split Completion transaction onto the I/O bus that includes the data. As part of the Split Completion transaction, the targeted device also provides the device number, function number and selected tag value previously specified by the requesting device so that the requesting device can match up the Split Completion transaction with its earlier read request. If the targeted device cannot complete the delivery of the data due some type of error, it returns a Split Completion Message, indicating that an error occurred.
The PCI-X bus standard represents a significant improvement over the conventional PCI standard. Nonetheless, an I/O bridge interfacing to a PCI-X bus can still constitute a bottleneck, especially in a computer system having a large number of peripheral devices. For example, the processors of an SMP computer system often move data in large, e.g., 64-byte, blocks. Suppose a given processor issues a write transaction to a peripheral device, such as a tape drive, and that the write transaction includes four 64-byte blocks of data. The processor sends each 64-byte block to the I/O bridge for delivery to the tape drive. If the tape drive and/or I/O bus can only accept DWORD transactions (i.e., 32-bit data blocks), each 64-byte block must be broken down into sixteen 32-bit DWORD blocks, which can then be individually driven onto the I/O bus.
As the tape drive can theoretically respond to each DWORD transaction with a Split Response instead of completing the write immediately, the I/O device assigns a different tag value to each DWORD. In this way, the I/O bridge can match up subsequent Split Completions with the particular DWORD being requested. Because the tag field 110 is 5-bits in length, the maximum number of split transactions that the I/O bridge can have outstanding at any given time is 32. For computer systems having only a few processors and only a few peripheral devices, this is deemed a sufficient number of outstanding split transactions.
For large computer systems, such as SMP systems, supporting large numbers of peripheral devices, however, this number has proven to be inadequate. Indeed, after receiving the second 64-byte block of data from the processor, the I/O bridge in the above example must stall the processor to prevent it from sending any further blocks of data until the tape drive completes enough DWORD transactions to free up sufficient tag values. Stalling a processor obviously reduces system performance.
Briefly, the present invention is directed to a system and method for increasing the number of split transactions that can be outstanding on an input/output (I/O) bus operating in accordance with a bus protocol, such as the Peripheral Component Interface Extended (PCI-X) specification standard. More specifically, an I/O bridge interfaces between one or more processors and memory subsystems, and one or more I/O devices coupled to the I/O bus. The I/O bridge includes a transaction initiation engine, a transaction completion engine and one or more queues for buffering information that is to be transferred onto or which has been received from the I/O bus. To initiate a bus transaction targeting a given I/O device, the transaction initiation engine generates an attribute message which it drives onto the bus. The attribute message includes a tag field and a function number field. In accordance with the invention, the transaction initiation engine concatenates, at least logically, the tag field and the function number field so as create a novel, super-tag field. For each bus transaction, the I/O bridge loads the super-tag field with a different value so as to keep track of transactions responded to with a Split Response by the targeted device. Creation of the super-tag allows the I/O bridge to support up to 256 outstanding split transactions.